Futurebus+ is an IEEE specification for backplane-based computing that permits architectural consistency across a broad range of computer products. Key attributes of Futurebus+ are discussed in the article of J. Theus appearing in Microprocessor Report, Volume 6, Number 7, May 27, 1992. Futurebus+ is a comprehensive architectural specification designed as an open standard; that is, an interface standard for which there are no preconceived restrictions in terms of architecture, microprocessor, and software implementations. It is also designed to support multiple generations of computer technology, leading to system speeds significantly greater than current systems.
Futurebus+ provides a 64-bit architecture with a compatible 32-bit subset and data path extensions to 128 or 256 bits. The protocols, while providing headroom for system growth, explicitly support real-time scheduling, fault tolerance, and high-availability and high-reliability systems.
The logical layering of the Futurebus+ specifications offers a wealth of architectural features with which designers may implement a wide variety of systems. Both loosely coupled and tightly coupled compute paradigms are supported via the parallel protocols and in the message-passing and cache-coherence protocols. The control and status registers provide a standard software interface to the Futurebus+, easing the development and transportability of I/O drivers and other system software.
Unlike older standard buses, Futurebus+ is optimized for a backplane environment. Backplane transceiver logic (BTL) circuits provide incident-wave switching capability (thus no stop and hold times), low capacitance with high current drive capability, and controlled one-volt voltage swings for fast switching.
Interface circuits connect local buses to system buses such as Futurebus+. New interface circuits are needed to connect local buses to backplane buses like Futurebus+. It is accordingly an object of the invention to provide a bus interface circuit for connecting a local bus to a standard system bus architecture. It is also an object of the invention to provide a method of connecting a backplane system bus to a local bus.
There are many advantages of the invention. First, the universal address generator is compatible with dual bus architecture. Additionally, the circuit can be implemented in standard cell technology, providing system design time reduction, program risk reduction, a greater degree of integration, greater specification complexity, and joint development opportunities.
Other objects and advantages of the invention will become apparent to those of ordinary skill in the art having reference to the following specification together with the drawings herein.